外贸新人，COA 学习制作

首先要了解COA 是什么意思？CERTIFICATE OF ANALYSIS 的缩写就是COA。就是产品分析证明，或者产品成分证明。

COA 能够让客人对我们的产品比较了解。

化工品做COA ，如果要做的产品，刚好有工厂的出场检验报告，那么可以以出厂检验报告为准，进行制作。如果没有就自己动手，丰衣足食。

以我公司的主营产品为例。

产品名复合肥NPK12-12-17+2MgO（复混肥NPK 12-12-17+2MgO)

英文名字：compound NPK 12-12-17+2MgO

第一步 要做的就是查这个产品的国家标准。复合肥的国家标准 GB1503-2002(从20xx年开始此产品有新标准GB1503-2009，我们认为旧标准对客人比较有利，客人也比较习惯就用旧标准)。

有些产品没有国家标准，可以参考部门标准，比如农业部标准，或者参考行业标准，或者参考企业标准。

此产品的标准 在标准文书第二页里面有，（标准是我们制作COA 的重要依据） 高浓度 中浓度 低浓度 Total nuitrent（N+P2O5+K2O）≥ 40 30 25

The rate of effective P2O5 ≥ 70 50 40

Moisture（H2O） ≤ 2 2.5 5

size（1.00-4.75mm or 3.35-5.60mm） ≥ 90 90 80

1 组织产品的单一养分含量不得低于4.0%，且单一养分测定值与标明值负偏差的绝对值不得大于1.5%。

2 以钙镁磷肥等枸溶性磷肥为基础磷肥并在包装容器上注明为“枸溶性磷”，可不控制“水溶性磷占有效磷百分率”指标。若为氮、钾二元肥料，也不控制“水溶性磷占有效磷百分率”指标。

第二步 因为一个标准里面可能会列出这种产品的几种型号。所以我们要结合自己的产品找对型号。

第三步 准备一个有公司抬头的电子文档，开始制作COA，列出此产品涉及到得主要指标。

复合肥NPK12-12-17 涉及到得指标，有N 含量，P2O5 含量，K20 含量，总养分含量，水溶性P2O5 含量，水分含量，颗粒大小。

那么我会列出 以下3列标准

TEST Specification(%)

1 Appearance Blue Granular（这一条是根据需要自己补充的）

2 Total N 12.0

3 P2O5 12.0

4 K2O 17.0

5 Total(N+P2O5+K2O) 41.0%

6 Moisture 2.0

7 Size 2-5mm

第四步 把检测结果补上

TEST Specification(%) Test(%)

1 Appearance Blue Granular Blue Granular

2 Total N 12.0 12.1

3 P2O5 12.0 12.0

4 K2O 17.0 17.0

5 Total(N+P2O5+K2O) 41.0% 41..1

6 Moisture 2.0 1.5

7 Size 2-5mm 2-5mm

检测结果这里是最重要的。我7项指标里面 2345 大于标准值都是好事，所以写的时候都写的比标准值大一点。如第二项12.0，检测结果写12.1.

第6项水分是低于2%，那么检测结果要写小于2%。

一个要求就是检测结果能证明你的产品是符合标准的合格产品。

做COA 还是挺简单的，多试几次就可以了。自己动手，不用每次生意还没做就要麻烦工厂，那多麻烦。

第二篇：COA

COA考试资料

前二章作业

1. 计算机的四个基本功能（Functions）是什么？(P6带圆点处)

2. 在计算机的top-level structure view中，四个structural components 是什么？P10 Figure 1.4

3. 谁提出了 store-program concept ?(P17)你能用汉语简单地描述这个存储程序的概念吗？

4. CPU的英文全称是什么(P9)？汉语意义是什么？P11 CPU构造 Figure 1.5

5. ALU的英文全称是什么？汉语意义是什么？(P9)

6. Von Neumann 的IAS机的五大部件都是什么？(P20带圆点处)

7. 在第一章中我们认识到的四个结构性部件（第2题）与Von Neumann的IAS机（第6题）中部件有本质差别吗？

8. Fundamental Computer Elements 有哪几个（P28 figure

2.6）？它们与计算机的四个基本功能的关系是什么？

9. Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？(P24 double every 18 months)

10. 本书的次标题和第二章第二节标题均为“Designing for Performance”,Performance 主要指什么(P37 带圆点处)？Performance Balance的（balance）平衡要平衡什么（P38）？

11. 本书作者将他要研究的范围局限在“desktop,

workstation , server“中，它们的中文名称是什么(桌面体、工作站和服务器)？各自的工作范围是什么？(P37)

Chapter 3 Homework

1.PC means _

A. personal computer B. programming controller

C. program counter D. portable computer

PC——存放下一条指令的地址（address of next instruction） MAR——存放本条指令的地址(address of the instruction) MBR——存放取得的内容(comtents )

2. PC holds A

A. address of next instruction B. next instruction

C. address of operand D. operand

3. At the end of fetch cycle, MAR holds ___(P54 fetch cycle 的步骤，对应12章的内容P422)

A. address of instruction B. instruction

C. address of operand D. operand

4. Interrupt process steps are __P61（相当重要）

A. suspending , resuming , branching & processing

B. branching , suspending , processing & resuming

C. suspending , branching , processing & resuming

D. processing , branching , resuming & suspending

5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .（未带符号）

A. 0 to n-1 B. 1 to n C. 0 to 2n-1 D. 1 to 2n

6.The length of the address code is 32 bits, so addressing range (or the range of address) is ________________. (1K=210B 1M=210K 1G=210M)

A. 4G B.from –2G to 2G C.4G-1 D. from 1 to 4G

7.There are three kinds of BUSes. Which is not belong to them?(P70 Figure 3.16)

A. address bus B. system bus

C. data bus D. control bu

第四章

一：选择题

1. The computer memory system refers to __(P97 区分Internal Memory和External memory)_

A. RAM Internal Memory(内部存储器)——register,main memory,ache

B. ROM External memory（外部存储器）——disk

C. Main memory

D. Register , main memory, cache, external memory

2. If the word of memory is 16 bits, which the following answer is right ?

A. The address width is 16 bits

B. The address width is related with 16 bits

C. The address width is not related with 16 bits

D. The address width is not less than 16 bits

3. The characteristics of internal memory compared to external memory(P100 figure 4.1 图中从上往下看：速度变慢，容量增大，单位成本降低)

A. Big capacity, high speed, low cost

B. Big capacity, low speed, high cost

C. small capacity, high speed, high cost

D. small capacity, high speed, low cost

4．On address mapping of cache, any block of main memory can be mapped to

any line of cache, it is （P107~117 ）

总结映射：Direct Mapping——fixed main memory be mapped to fixed line of cache

Associative Mapping——any block of main memory can be mapped to any line of cache,

Set Associative Mapping——the data in any block of main

A) Associative Mapping B) Direct Mapping

C) Set Associative Mapping D) Random Mapping

P118 总结写策略：write through——as well as to cache

Write back——when the difference between cache and main memory is found

5. Cache’s write-through polity means write operation to main memory _______.

A) as well as to cache

B)only when the cache is replaced

C)when the difference between cache and main memory is found

D) only when direct mapping is used

6. Cache’s write-back polity means write operation to main memory ______________.

a) as well as to cache

b) only when the relative cache is replaced

c) when the difference between cache and main memory is found

d) only when using direct mapping

7. On address mapping of cache, the data in any block of main

memory can be mapped to fixed line of cache, it is _________________.

A) associative mapping B) direct mapping

C) set associative mapping D) random mapping

8.On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is _________________.

B)associative mapping B) direct mapping

D) set associative mapping D) random mapping

二：计算题(from page 126)

Problem 4.1 , Problem 4.3 , Problem 4.4 , Problem 4.5 , , Problem 4.7, Problem 4.10

第五章作业

1.which type of memory is volatile?(P140 Table 5.1 熟记此表)

A.ROM B. E2PROM C. RAM D. flash memory

2.which type of memory has 6-transistor structure?（P141 Figure

5.2(b)）

DRAM——is made with cells that store data as charge on capacitors (read refresh circuits but slower)

SRAM——binary values are stored using traditional flip-flop logic-gate configurations(faster & does not need refresh circuits)

A. DRAM B. SRAM C. ROM D. EPROM

3.Using hamming code, its purpose is of one-bit error. (P150第二段)

A. detecting and correcting B. detecting C. correcting D. none of all

4.Flash memory is （同1） .

A. read-only memory B. read-mostly memory C. read-write memory D. volatile

5.Which answer about internal memory is not true? （P139）

A. RAM can be accessed at any time, but data would be lost when power down..

B. When accessing RAM, access time is non-relation with storage location.

C. In internal memory, data can’t be modified.

D. Each addressable location has a unique address.

Page161 Problems: 5.4 5.5 5.6 5.7 5.8

第六章作业

一、选择题

P180~183

RAID0——四个数据盘：不能纠错

RAID1——四个数据盘和四个copy盘：have copy ,mirror disk that contains the same data

RAID2——四个数据盘和三个校验盘：make use lf a parallel access technique(have copy)

RAID3——四个数据盘和一个校验盘：(同2)+only a single redundant （只要知道有错误，无需其位置）

RAID4——四个数据盘和一个校验盘：make use of RAID5——distributes the parity strips across all disks

RAID6——two different parity calculations are carried out and stored in separate blocks on different disks

1. RAID levels_________make use of an independent access technique.

A. 2 B. 3 C. 4 D. all

2. In RAID 4, to calculate the new parity, involves _ reads_P183.(two reads & two writes )

A. one B. two C. three D.four

3. During a read/write operation, the head is ------P164最后一段

A. moving B. stationary C. rotating D. above all

4. On a movable head system, the time it takes to position the head at the track is know as______.总结：（P171）seek time——the time it takes to position the head at the track

Rotational delay——the time it takes for the beginning of the sector to reach the head

Access time—the time it takes to get into position to read or write

A. seek time B. rotational delay C. access time D. transfer time

5. RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.（P175 相关的1，2，3 点内容）

A. parity B. user data C. OS D. anyone

6. Recording and retrieval via _________called a head（P167）

A. conductive coil B. aluminium C. glass D. Magnetic field

7.In Winchester disk track format, _________is a unique identifier or address used to locate a particular sector.

总结：ID field is a unique identifier or address used to locate a particular sector.

byte is a special bit pattern that delimits the beginning of the field

Data field holds data

Disk Data Layout:Sectors ,Tracks ,Intersector gap (各自的功能P165~166)

A. SYNCH B. Gap C. ID field D. Data field

8. Data are transferred to and from the disk in ________.

A. track B. sector C. gap D. cylinder

9. In _________, each logical strip is mapped to two separate physical disk.

A. RAID 1 B. RAID 2 C. RAID 3 D. RAID 4

10. With _________, the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.

A. RAID 1 B. RAID 2 C. RAID 3 D. RAID 4

11. The write-once read-many CD, known as ___(P184~187)

A. CD-ROM B. CD-R C. CD-R/W D. DVD

总结：CD/CD-ROM——read only ,CD-R——write only ,CD-RW——write many

DVD——read only

第七章

总结：Programmed I/O（P205）——CPU periodically reads & checks the status of I/O module until it find that the operation is complete

INTERRUPT-DRIVEN I/O——（P209 11个步骤）processor to issue an I/O command to a module and then go on to do

some other useful work

DMA（direct memory access）——the latter technique is more common and is referred to as the DMA module in effect steals a bus cycle

1. “When the CPU issues a command to the I/O module, it must wait until the I/O operation is complete”. It is programmed I/O , the word “wait” means ___

a. the CPU stops and does nothing b. the CPU does something else

c. the CPU periodically reads & checks the status of I/O module d. the CPU wait the Interrupt Request Signal

2. See Figure 7.7. To save (PSW & PC) and remainder onto stack, why the operations of restore them is reversed? Because the operations of stack are __

a. first in first out b. random c. last in first out d. sequenced

3. Using stack to save PC and remainder, the reason is _______P209~210 figure 7.7

a. some information needed for resuming the current program at the point of interrupt

b. when interrupt occurs, the instruction is not executed over, so the instruction at the point of interrupt must be executed once again

c. the stack must get some information for LIFO

d. the start address of ISR must transfer by stack

4. The signals of interrupt request and acknowledgement exchange between CPU and requesting I/O module. The reason of CPU’s acknowledgement is _____P210 第3步

a. to let the I/O module remove request signal b. to let CPU get the vector from data bus

c. both a & b d. other aims

5. In DMA , the DMA module takes over the operations of data transferring from CPU, it means _--P216（抓住关键词 cycle stealing）第一段+带圆点处

a. the DMA module can fetch and execute instructions like CPU does

b. the DMA module can control the bus to transfer data to or from memory using stealing cycle technique

c. the DMA module and CPU work together(co-operate) to transfer data into or from memory

d. when DMA module get ready, it issues interrupt request

signal to CPU for getting interrupt service

6. Transfer data with I/O modules, 3 types of techniques can be used. Which one is not belong them? P204

a. Interrupt-driven I/O b. programmed I/O c. direct I/O access d. DMA

Programmed I/O——sending a read or write command,and transferring the data

Interrupt-driven I/O——extracting data from main memory for output and storing data in main memory for input

DMA——I/O module and main memory exchange data directly,without processor involvement

7. Think 2 types of different data transferring, to input a word from keyboard and to output a data block of some sectors to harddisk. The best choice is to use ___P204

a. interrupt-driven I/O and DMA b. DMA and programmed I/O C. both interrupt-driven I/Os d. both DMAs

programmed I/O——read/write one word one time interrupt-driven I/Os——read/write a block of data DMA——read/write a block of data

8. Comparing with interrupt-driven I/O, DMA further raises the usage rate of CPU operations, because ___P209 P219

a. it isn’t necessary for CPU to save & restore scene b. it

isn’t necessary for CPU to intervene the dada transfer

c. it isn’t necessary for CPU to read & check status repeatedly d. both a and b

DMA 与 Programmed I/O比较则选C

第九章

1.Suppose bit long of two’s complement is 5 bits, which

arithmetic operation brings OVERFLOW? P288 (-2n-1~2n-1-1)

A. 5+8 B. (-8)+(-8)

C. 4-(-12) D.15-7

2.Overflow occurs sometime in ______arithmetic operation.P293

A. add B. subtract

C. add and subtract D. multiply

3. In twos complement, two positive integers(正整数) are added, when does overflow occurs?(同号相加，如果符号相反则 overflow) P293

A. There is a carry B. Sign bit is 1

C. There is a carry, and sign bit is 0 D. Can’t determine

4. An 8-bit twos complement 1001 0011 is changed to a 16-bit that equal to____.(n位码变为m位码，只需将原符号位向左重复写（m-n）位)

A.1000 0000 1001 0011 B. 0000 0000 1001 0011

C.1111 1111 1001 0011 D.1111 1111 0110 1101 11

5. An 8-bit twos complement 0001 0011 is changed to a 16-bit that equal to____.（同4）

A. 1000 0000 1001 0011 B. 0000 0000 0001 0011

C. 1111 1111 0001 0011 D. 1111 1111 1110 1101

6.Booth’s algorithm is used for Twos complement ___P301 Block Diagram of Hardware for Addition and

Subtraction P296 figure9.6

Flowchart for Unsigned Binary Multiplication P298 figure9.9

Booth's Algorithm for Twos complement P301 figure

9.12

Flowchart for Unsigned Binary Division P305 figure

9.16

A. addition B. subtraction

C. multiplication D. division

7. In floating-point arithmetic, addition can divide to 4 steps: ______.

A. load first operand, add second operand, check overflow and store result

B. compare exponent, shift significand, add significands and normalize

C. fetch instruction, indirectly address operand, execute instruction and interrupt

D. process scheduling states: create, get ready, is running and is blocked

8. In floating-point arithmetic, multiplication can divide to 4 steps: ______.

A. load first operand, add second operand, check overflow and store result

B. fetch instruction, indirectly address operand, execute instruction and interrupt

C. process scheduling states: create, get ready, is running and is blocked

D. check for zero, add exponents, multiply significands, normalize, and round.

9.The main functions of ALU are?

A. Logic B. Arithmetic

C. Logic and arithmetic D. Only addition

10. Which is true?

A. Subtraction can not be finished by adder and complement circuits in ALU

B. Carry and overflow are not same

C. In twos complement, the negation of an integer can be formed with the following rules: bitwise not (excluding the sign bit), and add 1.

D. In twos complement, addition is normal binary addition,

but monitor sign bit for overflow

Chapter 10 and Chapter 11(寻址方式)

P（383）Table 11.1 Basic Addressing Modes (disadvatage & advatage) ——no memory access in execution cycle ,very fast,but value range limited and operand no-normal

——one times memory access in execution cycle,but address length(range) limited

——two times memory access (slow), operand normal ,value range non-limited,address length(range) non-limited

——no memory access(fast),operand normal(value no limited),address length limited(address range very litter )

——one times memory access operand normal(value range non-limited

times ),address memory length non-limited(address length very large) ——one access(value

non-limited),address calculation complex

1: In instruction, the number of addresses is 0, the operand(s)’ address is implied, which is(are) in_______.p334 addresses is 1——a second address must be implicit to AC

addresses is 2——one address does double duty both an operand and a result

addresses is 3——one address ,two operands

A. accumulator B. program counter

C. top of stack D. any register

2: Which the following addressing mode can achieve the target of branch in program?(p387)

A. Direct addressing mode

B. Register addressing mode

C. Base-register addressing mode

D. Relative addressing mode

3: In index-register addressing mode , the address of operand is equal to

A. The content of base-register plus displacement

B. The content of index-register plus displacement

C. The content of program counter plus displacement

D. The content of AC plus displacement

4: The address of operand is in the instruction, it is_________ ?

A. Direct addressing mode

B. Register indirect addressing mode

C. Stack addressing mode

D. Displacement addressing mode

5: Which the following is not the area that the source and result operands can be stored in ?(p331)

A. Main or virtual memory

B. CPU register

C. I/O device

D. Instruction

6: Compared with indirect addressing mode , the advantage of register indirect addressing mode is

A. Large address space

B. Multiple memory reference

C. Limit address space

D. Less memory access

7:With base-register ADDRESSING , the ______________ register can be used.

A. BASE B. INDEX Relative addressing——PC

C. PC D. ANY Indexing——Index-Register

8:The disadvantage of INDIRECT ADDRESSING is ____________.

A. large addressing range B. no memory access

C. more memory access D. large value range 9:Which is not an advantage with REGISTER INDIRECT?

A. just one times of operand’s access B. large memory space

C. large value range D. no memory reference

10:The REGISTER ADDRESSING is very fast, but it has _________________.

A. very less value range B. very less address space

C. more memory access D. very complex address’ calculating

11:The disadvantage of IMMEDIATE ADDRESSING is ___________.

A. limited address range B. more memory access

C. limit value range D. less memory access

12:In instruction, the number of addresses is 2, one address does double duty both _______________.

A. a result and the address of next instruction

B. an operand and a result

C. an operand and the address of next instruction

D. two closed operands

13.In instruction, the number of addresses is 3, which are ____

A. two operands and one result

B. two operands and an address of next instruction

C. one operand, one result and an address of next instruction

D. two operands and an address of next instruction

14.The address is known as a type of data, because it is represented by ___(p337)

Address——unsigned integers

Numbers——integer or fixed point ,fleating point, decimal

A. a number of floating point B. a signed integer

C. an unsigned integer D. a number of hexadecimal

15.Which is not a feature of Pentium .

A. complex and flex addressing B. abundant instruction set

C. simple format and fixed instruction length D. strong support to high language

16. Which is not a feature of Power PC .

A. less and simple addressing mode B. basic and simple instruction set

C. variable instruction length and complex format D. strong support to high language

Chapter 12 and Chapter 18

1. After the information flow of fetch subcycle, the content of MBR is_____________.

A.oprand B.address of instruction C. instruction D. address of operand

2. After the information flow of instruction subcycle, the content of MBR is_____________.

A.oprand B.address of instruction C. instruction D. address of operand

3. The worse factor that limits the performance of instruction pipeline is _________________.

A.conditional branch delaying the operation of target address

B. the stage number of pipeline can’t exceed 6

C. two’s complement arithmetic too complex

D. general purpose registers too few

4.The most factor to affect instruction pipeline effectiveness is __________.

A. The number of stages B. the number of instruction

C. the conditional branch instruction D. the number of pipelines

5. RISC rejects ______.(p463带圆点)

A. few, simple addressing modes

B. a limited and simple instruction set

C. few, simple instruction formats

D. a few number of general purpose registers

6. RISC rejects ______.（同上题）

A.a large number of general-purpose registers

B. indirect addressing

C. a single instruction size

D. a small number of addressing mode

7. Which is NOT a characteristic of RISC processor.

A. a highly optimized pipeline. B. Register to register operations

C. a large number of general-purpose registers D. a complexed instruction format

8. Control unit use some input signals to produce control signals

that open the gates of information paths and let the

micro-operations implement. Which is NOT the input signals of control unit/ P585（带圆点）+P594（input signals——instruction register,the clock,flags,and control bus signals——interrupt signals and acknowledgments）

A.clock and flags B.instruction register C.interrupt request signal D.memory read or write

9. Control unit use some output signals to cause some

operations. Which is not included in the output signals?（P585 control signals within the processor and control signals to control bus)

A.signals that cause data movement

B.signals that activate specific functions(e.g. add/sub/…)

C.flags

D.read or write or acknowledgement

10. Symmetric Multi-Processor (SMP) system is tightly coupled by _(p646~647

NUMA—— interconnect network and distributed memory)

A. high-speed data-link and distributed memory

B. shared RAIDs and high-speed data-link

C. distributed caches and shared memory

D. interconnect network and distributed memory

11. The SMP means __________.（P647）

SISD means single instruction,single data stream SIMD means single instruction,multiple data stream

MIMD means multiple instruction,multiple data stream

A.Sharing Memory Processes B.Split Memory to Parts

D.Stack and Memory Pointer D.Symmetric

Multi-Processor

12.The “MESI” means states of ____________ .(P659)

A.Modified, Exclusive, Stored and Inclusive

B.Modified, Expected, Shared and Interrupted

C.Modified, Exclusive, Shared and Invalid

D.Moved, Exchanged, Shared and Invalid

13.The protocol “MESI” is also called ____(P659 )many readers but only one writer at a time

A. write back policy B. write-update protocol

C. write-invalidate protocol D. write through policy

Chapter 12

1. Which register is user –visible but is not directly operated in 8086 ?(p419 图（b）)

A. DS B. SP C. IP D. BP

2. The indirect sub-cycle is occurred _____________ ?（P420）Interrupt cycle 在Execute cycle 之后

A. before fetch sub-cycle B. after execute sub-cycle C. after interrupt sub-cycle

D. after fetch sub-cycle and before execute sub-cycle

3. Within indirect sub-cycle , the thing the CPU must do is ______________?

A. fetch operand or store result B. fetch operand’s address from memory

C. fetch next instruction from memory D. nothing

4. In general, which register is used for relative addressing ---- the content in this register plus the A supplied by instruction to make a target address in branch or loop instructions.（P387）

A. SP（stack pointer） B. IR(inex-register) C. BR(base register) D. PC

5. The Memory Address Register connects to ____________ BUS . (MBR_DATA BUS)

A. system B. address C. data D. control

6. The Memory Buffer Register links to ________ BUS.

A. system B. address C. data D. control

7. After Indirect cycle , there is a ______________ cycle .(p420

Figure 12.4)

A. Fetch B. Indirect C. Execute D. Interrupt

8. The Interrupt cycle is __________ ______ Execute cycle .(同上题)

A. always after B. never after C. sometime after D. maybe before

9. The correct cycle sequence is _________________ .（同上）

A. Fetch , Indirect , Execute and Interrupt B. Fetch , Execute , Indirect and Interrupt

C. Fetch , Indirect , Interrupt and Execute D. Indirect , Fetch , Execute and Interrup

10. The aim of the indirect cycle is to get __________________.

A. an operand B. an instruction C. an address of an instruction D. an address of an operand

11. Which is not in the ALU ?（P414 figure 12.2）

A. shifter B. adder C. complementer D. Accumulator

12. The registers in the CPU is divided _____registers and ________registers .(P414 带圆点)

A. general purpose , user-visible B. user-visible（P415） , control and status（P416）

C. data , address D. general purpose ,

control and status

13. The Base register is a(n) __________ register in 8086.（P419 figure 12.3）

A. general purpose B. data C. address D. control

14. The Instruction Pointer is a(n) __________ register in 8086.

A. general purpose

B. data C. address D. control