EDA实习报告

时间：2024.3.31

北华大学EDA实习报告

实习名称：运算电路设计

专业：电子信息科学与技术

班级：电子11-1

学号：20111601010109

姓名：李亮

实习日期：2014/3/10-21

前言

本文介绍了一个简单的计算器的设计，该设计采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示LCD1602上。系统由计算部分、输入部分、选择部分、输出部分组成，计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真，并下载到试验箱,用实验箱上的按键开关模拟输入，用LCD显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能，其结果简单，易于实现。

一．实验目的与要求... 3

二．流程图... 4

三。软件介绍……………………………………………………………………………………….4

四．各个模块... 5

(1)加法器模块... 5

1、加RTL图... 5

2、加法器程序... 6

3程序说明……………………………………………………………………………… 6

（2）减法器模块... 6

1、减RTL图... 9

2、减法器程序... 6

3程序说明……………………………………………………………………………. 8

（3）乘法器模块... 8

1乘RTL图... 8

3、乘法器程序... 9

3、程序说明... 9

（4）除法器模块... 9

1、除RTL图... 9

2、除法器程序... 9

3、程序说明... 10

（5）LCD1602显示结果总程序含选择模式... 10

1、总RTL图... 11

2、程序... 11

3、程序说明... 20

五．实习心得... 21

一．实验目的与要求

1、熟悉QuartusII软件的相关操作，掌握数字电路设计的基本流程。

2、介绍QuartusII的软件，掌握基本的设计思路，软件环境参数配置，仿真，管脚分配，下载等基本操作。

3、了解VHDL或原理图设计方法。

4、掌握并行加法器，减法器乘法器以及除法器的设计思路及工作原理。

5、设计一个能完成加减乘除功能并以十进制在LCD上显示结果运算速度为1KHZ的简单计算器。

二、流程图

三．软件介绍

QuartusⅡ是Altera提供的FPGA/CPLD开发集成环境，Altera是世界上最大的可编程逻辑器件供应商之一。QuartusⅡ在21世纪初推出，是altera前一代FPGA/CPLD集成开发环境MAX+PLUSⅡ的更新换代产品，其界面更好，使用便捷。在QuartusⅡ上可以完成1.5节以上所述的整个流程，它提供了一种与结构无关的设计环境，使设计者能方便的进行设计输入，快速处理和器件编辑。

四．各个模块

(1)加法器模块

加的RTL图：

加法源程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADDER4B IS

PORT(

CLR:IN STD_LOGIC;

A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END;

ARCHITECTURE behave OF ADDER4B IS

SIGNAL SINT,AA,BB:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(CLR,A,B)

begin

if CLR='1' THEN AA<="00000000";BB<="00000000";

ELSE

AA<="0000"&A;

BB<="0000"&B;

END IF;

END PROCESS;

SINT<=AA+BB;

S<=SINT;

END behave;

说明：

当CLR为‘1’时清零，输出为零

当CLR为‘0’时，输入两个四位二进制数，输出两个数之和，S[3..0]为和，S[4]为进位。

（2）减法器模块

减法RTL图

减法源程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADD IS

PORT(

CLR:IN STD_LOGIC;

A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT:OUT STD_LOGIC);

END ADD;

ARCHITECTURE behave OF ADD IS

SIGNAL SINT,AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN

PROCESS(CLR)

begin

if CLR='1' THEN AA<="00000";BB<="00000";

ELSE

AA<="0"&A;

BB<="0"&B;

END IF;

END PROCESS;

SINT<=AA+BB;

S<=SINT(3 DOWNTO 0);

COUT<=SINT(4);

END behave;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SUB4 IS

PORT(CLR:IN STD_LOGIC;

A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CO:OUT STD_LOGIC);

END SUB4;

ARCHITECTURE BEHAVE OF SUB4 IS

COMPONENT ADD IS

PORT(CLR:IN STD_LOGIC;

A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT:OUT STD_LOGIC);

END COMPONENT;

SIGNAL C,C1:STD_LOGIC;

SIGNAL BB:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SS:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLR)

BEGIN

IF CLR='1' THEN

C<='1';

ELSE C<='0';

END IF;

END PROCESS;

BB(3 DOWNTO 0)<=NOT B(3 DOWNTO 0);

U:ADD PORT MAP (A=>A,B=>BB,CLR=>C,S=>SS,COUT=>C1);

PROCESS(C)

BEGIN

IF C='1' THEN S<="0000";CO<='0';

ELSE S<=SS+'1';CO<=NOT C1;

END IF;

END PROCESS;

END BEHAVE;

说明：

减去一个数等于加上这个数的补码。对减数求补码，再调用加器

当CLR为‘1’时清零，输出为零

当CLR为‘0’时，a是四位二进制被减数，b时四位二进制减数。S为相减的结果，co为借位，当co为0时代表a减b是整数，否则为负数或者0。

（3）乘法器模块

乘法的RTL图

乘法源程序

library IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MULTI4B IS

PORT(CLR:IN STD_LOGIC;

A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END MULTI4B;

ARCHITECTURE MULTI_ARCH OF MULTI4B IS

SIGNAL D0:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D1:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D2:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D3:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLR,A,B)

BEGIN

IF CLR='1' THEN Y<="00000000";

ELSE

IF B(0)='0' THEN D0<="0000"; ELSE D0<=A; END IF;

IF B(1)='0' THEN D1<="0000"; ELSE D1<=A; END IF;

IF B(2)='0' THEN D2<="0000"; ELSE D2<=A; END IF;

IF B(3)='0' THEN D3<="0000"; ELSE D3<=A; END IF;

Y<=("0000"&D0)+("000"&D1&"0")+("00"&D2&"00")+("0"&D3&"000");

END IF;

END PROCESS;

END MULTI_ARCH;

说明：

用并行相乘的方法。通过开关，两组分别输入4bit的数据进行乘法运算时，先求出部分积，即求得二进制数据的乘数和被乘数逐位相乘，之后运用二进制加法进行加和

当clr为‘1’时输出为0

当clr为‘0’时，a与b相乘输出y

（4）除法器模块

除法的RTL图

除法源程序

library IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DIVISION IS

PORT(CLR:IN STD_LOGIC;

A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END ENTITY DIVISION;

ARCHITECTURE ONE OF DIVISION IS

BEGIN

PROCESS(CLR,A,B)

VARIABLE E,F,G:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

IF CLR='1' THEN S<="00000000";

ELSIF B="0000" THEN S<="00000000";

ELSE F:=A; G:=B; E:=(OTHERS=>'0');

FOR I IN 1 TO 15 LOOP

IF(F>=G) THEN F:=F-G; E:=E+1;

ELSE EXIT;

END IF;

END LOOP;

S(7 DOWNTO 4)<=E;S(3 DOWNTO 0)<=F;

END IF;

END PROCESS;

END ONE;

说明：

当clr=‘1’时清零，当clr=‘0’时进行除法运算。

a、b为四位二进制数，a为被除数，b为除数，s高四位为商，s低四位为余数。

（5）利用LCD1602显示结果的运算总程序

总RTL图

源程序：

library IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY jisq IS

PORT(

CLR:IN STD_LOGIC;

MD :IN STD_LOGIC_VECTOR(1 DOWNTO 0);

A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

OUT1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

OUT2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

clk:in std_logic;

lcd_cs:out std_logic;

lcd_rs:out std_logic;

lcd_rw:out std_logic;

lcd_data:out std_logic_vector(7 downto 0);

lcd_blon:out std_logic);

END;

ARCHITECTURE BEHAV OF jisq IS

COMPONENT ADD IS

PORT(CLR:IN STD_LOGIC;

A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

S2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT:OUT STD_LOGIC);

END COMPONENT;

SIGNAL C,C1:STD_LOGIC;

SIGNAL BB0:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SS0:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SINT,AA,BB,Y,S,S0,S1,S3:STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL D0:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D1:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D2:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL D3:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL MMD:STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL E,F:STD_LOGIC_VECTOR(7 DOWNTO 0);

signal data_buf:std_logic_vector(9 downto 0);

signal v:std_logic_vector(26 downto 0);

signal vv:std_logic_vector(26 downto 0);

signal high1:std_logic;

signal low1:std_logic;

signal b1:std_logic_vector(2 downto 0);

BEGIN

PROCESS(CLR,A,B) --add

begin

if CLR='1' THEN AA<="00000000";BB<="00000000";

ELSE

AA<="0000"&A;

BB<="0000"&B;

END IF;

END PROCESS;

SINT<=AA+BB;

PROCESS(CLR) --sub

BEGIN

IF CLR='1' THEN

C<='1';

ELSE C<='0';

END IF;

END PROCESS;

BB0(3 DOWNTO 0)<=NOT B(3 DOWNTO 0);

U:ADD PORT MAP (A=>A,B=>BB0,CLR=>C,S2=>SS0,COUT=>C1);

PROCESS(C)

BEGIN

IF C='1' THEN S1(3 DOWNTO 0)<="0000";S1(4)<='0';

ELSE S1(3 DOWNTO 0)<=SS0+'1';S1(4)<=NOT C1;

END IF;

END PROCESS;

PROCESS(CLR,A,B) --mul

BEGIN

IF CLR='1' THEN Y<="00000000";

ELSE

IF B(0)='0' THEN D0<="0000"; ELSE D0<=A; END IF;

IF B(1)='0' THEN D1<="0000"; ELSE D1<=A; END IF;

IF B(2)='0' THEN D2<="0000"; ELSE D2<=A; END IF;

IF B(3)='0' THEN D3<="0000"; ELSE D3<=A; END IF;

Y<=("0000"&D0)+("000"&D1&"0")+("00"&D2&"00")+("0"&D3&"000");

END IF;

END PROCESS;

PROCESS(CLR,A,B) --div

VARIABLE E,F,G:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

IF CLR='1' THEN S0<="00000000";

ELSIF B="0000" THEN S0<="00000000";

ELSE F:=A; G:=B; E:=(OTHERS=>'0');

FOR I IN 1 TO 15 LOOP

IF(F>=G) THEN F:=F-G; E:=E+1;

ELSE EXIT;

END IF;

END LOOP;

S0(7 DOWNTO 4)<=E;S0(3 DOWNTO 0)<=F;

END IF;

END PROCESS;

PROCESS(CLR,MD)

BEGIN

IF CLR='1' THEN MMD <= "00";

ELSE MMD <= MD;

END IF;

END PROCESS;

PROCESS(MMD) --mode

BEGIN

IF MMD = "00" THEN S3 <= SINT;

ELSIF MMD = "01" THEN S3 <= S1;

ELSIF MMD = "10" THEN S3 <= Y;

ELSIF MMD = "11" THEN S3 <= S0;

END IF;

END PROCESS;

PROCESS( CLR,S3 ) --place

VARIABLE E,F,G:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF MMD < 3 THEN

IF CLR = '0' THEN F:=S3; G:="00001010"; E:=(OTHERS=>'0');

FOR I IN 1 TO 15 LOOP

IF(F>=G) THEN F:=F-G; E:=E+1;

ELSE EXIT;

END IF;

END LOOP;

S(7 DOWNTO 4)<=E(3 DOWNTO 0);S(3 DOWNTO 0)<=F(3 DOWNTO 0);

END IF;

ELSE S <= S3;

END IF;

END PROCESS;

process (clk,S)

begin

lcd_blon<='1';

if(clk'event and clk='1') then

if(v<201000) then

if(v=200100) then

data_buf(0)<='0';

end if;

v<=v+1;

else

v<="000000000000000000000000000";

if S(3 DOWNTO 0)="0000" then

lcd_blon<='1';

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001100001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0001" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001100011";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0010" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001100101";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0011" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001100111";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0100" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001101001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0101" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001101011";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0110" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001101101";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="0111" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001101111";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="1000" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001110001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(3 DOWNTO 0)="1001" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "110"=> data_buf<="0001110011";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0000" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0001" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100011";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0010" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100101";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0011" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001100111";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0100" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001101001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0101" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001101011";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0110" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001101101";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="0111" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001101111";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="1000" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001110001";b1<=b1+1;

when "111"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

if S(7 DOWNTO 4)="1001" then

case b1 is

when "000"=> data_buf<="1001110001";b1<=b1+1;

when "001"=> data_buf<="1000011001";b1<=b1+1;

when "010"=> data_buf<="1000001101";b1<=b1+1;

when "011"=> data_buf<="1110000001";b1<=b1+1;

when "100"=> data_buf<="1000000011";b1<=b1+1;

when "101"=> data_buf<="0001110011";b1<=b1+1;

when "110"=> data_buf<="0001100010";b1<=b1+1;

when others=>b1<="000";

end case;

end if;

end process;

process (clk)

begin

if(clk'event and clk='1') then

case data_buf(9) is

when '1'=>high1<='1';low1<='0';

when '0'=>high1<='0';low1<='1';

end case;

if(data_buf(0)='1') then

vv<=vv+1;

case vv is

when "000000000000000000000000010"=>lcd_rs<=high1;lcd_cs<='1';

when "000000000000000000000001010"=>lcd_rs<=low1;

when "000000000000000000000001111"=>lcd_cs<='1';

when "000000000000000000000011110"=>lcd_data<=data_buf(8 downto 1);

when "000000000110000110101100011"=>lcd_cs<='0';

when "000000000110000110101101101"=>lcd_rs<=high1;

when "000000000110000110101110111"=>lcd_cs<='1';

when others=>null;

end case;

else

vv<="000000000000000000000000000";

end if;

end process;

END BEHAV;

说明：

该程序采用多进程并行的方式进行编写具体包含了加，减，乘，除四个基本运算模块和选择模块及显示模块其中选择部分。

当输入为00时输出加法结果

当输入为01时输出减法结果

当输入为10时输出乘法结果

当输入为11时输出除法结果

实习心得

在这次实习的过程中，我觉得收获很多，在设计过程中，我锻炼了分析、解决问题的能力，并初步掌握了Quartus II的工作方式，并对硬件描述语言有了初步的认识，在完成过程中，关于运算电路的设计，有多种不同的实现方法但也遇见了很多的问题，经过和同学讨论并查阅相关资料，找到了简单易行的方法，同时学会了简单运用一些逻辑门电路，并最终在试验箱上运行出了想要的结果，虽然这次实习我只是简单的做出了一个简易运算器但毕竟是自己亲手操作完成的，还是觉得很有成就感。在整个过程中我还认识到了Quartus II软件功能的强大，知道了它在电路设计方面的巨大优势这也增加了我对数字电子技术的兴趣。

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