电 子 信 息 科 学 与 技 术
EDA课程设计报告
设计题目： 数字时钟的设计
班 级 ： 电子1201
一、 实验目的
学习并掌握数字钟的原理、设计方法。
二、 实验内容
计数始终由模60秒计数器、模60分计数器、模24小时计数器、报时模块、分，时校定模块及输出显示组成，可以采用同步计数器或异步计数器设计方法。
三、 实验要求
1、 计时范围为0小时0分0秒至23小时59分59秒。
2、 采用6个8段数码管分别显示小时十位，小时个位，分钟十位，分钟个位，秒十位，秒个位。
3、 整点报时，蜂鸣器响5声，每秒响一声。
4、校时功能能够单独校分，校时，校秒，用按键控制。
5、具有清零，启动，停止计数功能，用按键控制。
6、采用静态扫描方式显示。
四、 系统设计方案
1、 整个模块采用一个时钟，时钟的频率为一秒，用于程序秒的输入。
2、 时分秒皆采用两个位的计数，一位代表十位，一位代表个位。分秒为60进制，时为24进制。个
位逢九向十位进一，秒逢59向分进一，分逢59向时进一。
3、 在小时的子程序里把两位小时数转换成一位数作为报时程序的输入。
五、 主要VHDL源程序
主程序：主要将建好的模60秒计数器、模60分计数器、模24小时计数器、报时模块、分，时校定模块，译码模块连接起来。用的是端口映射方式。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity time1 is
--generic(N: integer :=60 );
port(
clk:in std_logic;
reset:in std_logic;
stop:in std_logic;
clock_out:out std_logic;
min_add:in std_logic;
hour_add:in std_logic;
secout_1:out std_logic_vector(6 downto 0);
secout_2:out std_logic_vector(6 downto 0);
min_out_1:out std_logic_vector(6 downto 0);
min_out_2:out std_logic_vector(6 downto 0);
hour_cout_1:out std_logic_vector(6 downto 0); hour_cout_2:out std_logic_vector(6 downto 0)
);
end entity time1;
architecture xtime1 of time1 is
--60s
component secoud is
port(
clk:in std_logic;
reset:in std_logic;
secout1:out integer range 0 to 9;
secout2:out integer range 0 to 9; --0 to 5 en_min:out std_logic
);
end component secoud;
--60min
component minute is
port(
en_min:in std_logic;
reset:in std_logic;
min_out1:out integer range 0 to 9;
min_out2:out integer range 0 to 9; --0 to 5 en_hour:out std_logic
);
end component minute;
--24hour
component hour is
port(
en_hour:in std_logic;
reset:in std_logic;
hour_cout1:out integer range 0 to 9;
hour_cout2:out integer range 0 to 9 --0 to 2
);
end component hour;
--yima
component decode_dis is
port(
din:in integer range 0 to 9;
dout:out std_logic_vector(6 downto 0)
);
end component decode_dis;
--huomen
component or_2 is
port(
a:in std_logic;
b:in std_logic;
c:out std_logic
);
end component or_2;
--div_stop
component div_stop is
port(
clk:in std_logic;
stop:in std_logic;
clk_out:out std_logic
);
end component div_stop;
--clock_bit
component clock_bit is
port(
min_in1:in integer range 0 to 9;
min_in2:in integer range 0 to 9;
sec_in1:in integer range 0 to 9;
sec_in2:in integer range 0 to 9;
clock_out:out std_logic
);
end component clock_bit;
signal s1:std_logic;
signal s2:std_logic;
signal s3:std_logic;
signal s4:std_logic;
signal clk_out:std_logic;
signal secout1:integer range 0 to 9;
signal secout2:integer range 0 to 9;-- 0 to 5; signal min_out1:integer range 0 to 9;
signal min_out2:integer range 0 to 9;-- 0 to 5; signal hour_cout1:integer range 0 to 9;
signal hour_cout2:integer range 0 to 9;-- 0 to 2;
begin
g1:for i in 0 to 12 generate
g2:if i=0 generate
hourx: hour port map (s4,reset,hour_cout1,hour_cout2); --24hour
end generate;
g3:if i=1 generate
minutex: minute port map (s2,reset,min_out1,min_out2,s3); --60min end generate;
g4:if i=2 generate
secoudx: secoud port map (clk_out,reset,secout1,secout2,s1); --60s
end generate;
g5:if i=3 generate
decode_dis1: decode_dis port map (hour_cout1,hour_cout_1); ----24hour yima1 end generate;
g6:if i=4 generate
decode_dis1: decode_dis port map (hour_cout2,hour_cout_2); ----24hour yima2 end generate;
g7:if i=5 generate
decode_dis2: decode_dis port map (min_out1,min_out_1); ----60min yima1 end generate;
g8:if i=6 generate
decode_dis2: decode_dis port map (min_out2,min_out_2); ----60min yima2 end generate;
g9:if i=7 generate
decode_dis3: decode_dis port map (secout1,secout_1); ----60s yima1 end generate;
g10:if i=8 generate
decode_dis3: decode_dis port map (secout2,secout_2); ----60s yima2 end generate;
g11:if i=9 generate
xxor_2: or_2 port map (min_add,s1,s2); ----huomen min add end generate;
g12:if i=10 generate
xxor_2: or_2 port map (hour_add,s3,s4); ----huomen hour add end generate;
g13:if i=11 generate
div_stop1: div_stop port map (clk,stop,clk_out); ----div_stop end generate;
g14:if i=12 generate
clock_bit1:clock_bit port map (min_out1,min_out2,secout1,secout2,clock_out);----clock_bit end generate;
end generate;
end architecture xtime1;
模60秒 秒个位逢9进一并归零，秒十位逢5进一并归零，完成60秒的计时。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--60s
entity secoud is
generic(N: integer :=10 );
port(
clk:in std_logic;
reset:in std_logic;
secout1:out integer range 0 to 9;
secout2:out integer range 0 to 9;--0 to 5
en_min:out std_logic
);
end entity secoud;
architecture xsecoud of secoud is
signal emin:std_logic;
begin
process(reset,clk) is
variable sec0:integer range 0 to 9;
variable sec1:integer range 0 to 9;
--signal emin:std_logic;
begin
if reset='1' then
emin<='0';
sec0:=0;
sec1:=0;
elsif clk'event and clk='1' then
if sec0=N-1 then --10-1
sec0:=0;
sec1:=sec1+1;
if sec1=N-4 then --10-4
sec1:=0;
emin<='1';
else
emin<='0';
end if;
else
sec0:=sec0+1;
sec1:=sec1;
emin<='0';
end if;
end if;
secout1<=sec0;
secout2<=sec1;
en_min<=emin;
end process;
end architecture xsecoud;
模60分 分个位逢9进一并归零，分十位逢5进一并归零，完成60分的计时。 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--60 minute
entity minute is
generic(N: integer :=10 );
port(
en_min:in std_logic;
reset:in std_logic;
min_out1:out integer range 0 to 9;
min_out2:out integer range 0 to 9;--0 to 5
en_hour:out std_logic
);
end entity minute;
architecture xminute of minute is
signal ehour:std_logic;
begin
process(reset,en_min) is
variable min0:integer range 0 to N-1;--10-1
variable min1:integer range 0 to N-1;
--variable ehour:integer range 0 to 1;
begin
if reset='1' then
ehour<='0';
min0:=0;
min1:=0;
elsif en_min'event and en_min='1' then
if min0=N-1 then --10-1
min0:=0;
min1:=min1+1;
if min1=N-4 then --10-4
min1:=0;
ehour<='1';
else
ehour<='0';
end if;
else
min0:=min0+1;
min1:=min1;
ehour<='0';
end if;
end if;
min_out1<=min0;
min_out2<=min1;
en_hour<=ehour;
end process;
end architecture xminute;
模24小时，先小时个位逢十进一给小时十位，再每次判断是否大于24，大于就都清零。 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--24 hour
entity hour is
generic(N: integer :=10 );
port(
en_hour:in std_logic;
reset:in std_logic;
hour_cout1:out integer range 0 to 9;
hour_cout2:out integer range 0 to 9 --0 to 2
);
end entity hour;
architecture xhour of hour is
begin
process(reset,en_hour) is
variable hour1:integer range 0 to N-1;
variable hour2:integer range 0 to N-1;
begin
if reset='1' then
hour1:=0;
hour2:=0;
elsif en_hour'event and en_hour='1' then
if hour1=N-1 then --10-1
hour1:=0;
hour2:=hour2+1;
else
hour1:=hour1+1;
hour2:=hour2;
end if;
if hour2*10+hour1>=24 then
hour1:=0;
hour2:=0;
end if;
end if;
hour_cout1<=hour1;
hour_cout2<=hour2;
end process;
end architecture xhour;
译码部分，将123456789译成二进制码，并能在数码管上显示。 library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
--yima
entity decode_dis is
--generic(N: integer :=60 );
port(
din:in integer range 0 to 9;
dout:out std_logic_vector(6 downto 0)
);
end entity decode_dis;
architecture xdecode_dis of decode_dis is
begin
process(din) is
begin
case din is
when 0 => dout<="1111110";
when 1 => dout<="0110000";
when 2 => dout<="1101101";
when 3 => dout<="1111001";
when 4 => dout<="0110011";
when 5 => dout<="1011011";
when 6 => dout<="1011111";
when 7 => dout<="1110000";
when 8 => dout<="1111111";
when 9 => dout<="1111011";
when others => dout<="0000000";
end case;
end process;
end architecture xdecode_dis;
暂停，开始，分频部分，加一个按键，按键按一次开始，再按一次就停止，同时输出的二分频的时钟信号。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div_stop is
generic(N: integer :=2 );
port(
clk:in std_logic;
stop:in std_logic;
clk_out:out std_logic
);
end entity div_stop;
architecture xdiv_stop of div_stop is
shared variable en_stop:integer range 0 to 2;
--signal temp:std_logic;
begin
process(stop) is
begin
if stop'event and stop='1'then
en_stop:=en_stop + 1;
end if;
if en_stop=N then
en_stop:=0;
end if;
end process;
process(clk) is
variable counter:integer range 0 to N-1;
begin
if en_stop= 0 then
clk_out<='0';
elsif en_stop= 1 then
if clk'event and clk='1' then
if counter=N-1 then
counter:=0;
else
counter:=counter+1;
end if;
if counter<N/2 then
clk_out<='0';
else
clk_out<='1';
end if;
end if;
end if;
end process;
end architecture xdiv_stop;
一个或门，加上按键，按键按下就产生高电平，或上其他信号就变成高电平，用来教时分加或十加。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity or_2 is
--generic(N: integer :=60 );
port(
a:in std_logic;
b:in std_logic;
c:out std_logic
);
end entity or_2;
architecture xor_2 of or_2 is
begin
c<= a or b;
end architecture xor_2;
整点报时，判断分十位，分个位都为0，秒十位也为0，在判断秒个位在0~9的情况，02468秒就响，13579秒不响。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock_bit is
--generic(N: integer :=2 );
port(
--clk:in std_logic;
min_in1:in integer range 0 to 9;
min_in2:in integer range 0 to 9;
sec_in1:in integer range 0 to 9;
sec_in2:in integer range 0 to 9;
clock_out:out std_logic
);
end entity clock_bit;
architecture xclock_bit of clock_bit is
begin
process(min_in1,min_in2,sec_in1,sec_in2) is
begin
if min_in1= 0 and min_in2= 0 and sec_in2= 0 then
if sec_in1>= 0 and sec_in1<=9 then
if sec_in1=0 then
clock_out<='1';
elsif sec_in1= 1 then
clock_out<='0';
elsif sec_in1= 2 then
clock_out<='1';
elsif sec_in1= 3 then
clock_out<='0';
elsif sec_in1= 4 then
clock_out<='1';
elsif sec_in1= 5 then
clock_out<='0';
elsif sec_in1= 6 then
clock_out<='1';
elsif sec_in1= 7 then
clock_out<='0';
elsif sec_in1= 8 then
clock_out<='1';
else
clock_out<='0';
end if;
else
clock_out<='0';
end if;
else
clock_out<='0';
end if;
end process;
end architecture xclock_bit;
六、 设计中遇到的问题与体会
首先是第一次用这种硬件描述语言来实际做一个时钟，当然会遇到好多的问题，比如实验开发板是怎样的，能怎样接起来，比如数码管怎样接，还有按键是怎样的一种触发机制，这是比较让我们为难的。
其次不知道怎样实现所要求的功能，没有一种实现的思路。
最后还有遇到下载不了程序到开发板的问题。
随着我们一步步的进行也就开始有了了解，于是做起来就有了思路，然后问了会的同学教了一下怎样下载程序到开发板上，然后慢慢的调式，终于有了结果，这次试验给我的体会是当遇到从来没有见到过的东西的时候也不必害怕，慢慢的去学他，不会的就问老师问会的同学，写程序没有思想可以参考别人的，然后想出自己的，这样才有进步，还有要好好跟同学们一起合作，团结就是力量。